Verilog: Add language support

Adding in base definition of verilog language for verilog language support.

Note verilog has two distinct formats (verilog and systemverilog) - however the two are sequential and verilog after 2005 has not been updated improved as a language, all efforts were put into systemverilog. So just identified this as one language that is backwards compatible based on the versions - note all versions of verilog and SystemVerilog are supersets of the preceeding version.

I've tested this with slang and verilator but none of the EDA commercial tools.

I do need some help identifying the version of the tool along with the some checks the tool can compile a simple testcase. Help Wanted !!!

Issue: #23387
Topic-rename: verilog-language-support